As the development of semiconductor technology, feature sizes of metal-oxide-semiconductor-field-effect transistors (MOSFETs) decrease continuously. The size decreasing of the MOSFETs causes a severe problem of gate current leakage. The gate leakage current can be reduced by using a high-K gate dielectric, which may have an increased physical thickness with a constant equivalent oxide thickness (EOT). However, conventional Poly-Si gate is incompatible with the high-K gate dielectric. Combination of a metal gate and the high-K gate dielectric not only avoids the exhaustion effect of the Poly-Si gate and decrease gate resistance, but also avoid penetration of boron and enhance device reliability. Therefore, the combination of the metal gate and the high-K gate dielectric is widely used in the MOSFETs. However, integration of the metal gate and the high-K gate dielectric is still confronted with many challenges, such as problems related to thermostability and interface state. Particularly, due to Fermi-Pinning Effect, it is difficult for the MOSEFT using the metal gate and the high-K dielectric to have an appropriately low threshold voltage.
In a complementary-metal-oxide-semiconductor (CMOS) device integrating an N-type MOSFET (NMOSFET) and a P-type MOSFET (PMOSFET), to obtain appropriate threshold voltages, the NMOSFET should have an effective work function near the bottom of the conduction band of Si (about 4.1 eV), while the PMOSFET should have an effective work function near the top of the valence band of Si (about 5.2 eV). Different combinations of the metal gate and the high-K dielectric may be selected respectively for the NMOSFET and PMOSFET, so as to realize required threshold voltages. As a result, dual metal gates and dual high-K dielectrics need to be formed in one chip. During manufacture of the CMOS device, usually multi-deposition, photolithography and etching steps for the metal gates and the high-K dielectrics gate stack are performed respectively for the NMOSFET and the PMOSFET. Therefore, the method for manufacturing semiconductor devices comprising the dual metal gates and the dual gate dielectrics is complicated and thus is not suitable for mass production, which further leads to high cost.